1. Field of the Invention
The present invention relates to a delay circuit and, more specifically, it relates to an inverter circuit which outputs an output signal delayed from an input signal.
2. Description of the Prior Art
In the conventional delay circuit, for example an inverter circuit having a complementary insulated gate device, a capacitor for waveform shaping is connected between an input and the power supply or between an input and the ground of the inverter circuit to obtain an output signal delayed from an input signal.
FIG. 1 is a schematic diagram showing one example of a conventional delay circuit having a complementary insulated gate device. The delay circuit having the insulated gate device shown in FIG. 1 comprises a MOS (Metal Oxide Semiconductor) capacitor C1 for waveform shaping and an inverter 30. The capacitor C1 is connected between an input terminal 1 and the power supply V.sub.cc. The inverter 30 comprises a series connection of a p type MIS Metal Insulator Semiconductor) filed effect transistor Q5 and an n type MIS field effect transistor Q6 connected between the power supply V.sub.cc and the ground V.sub.ss. Each of the gates of the transistor Q5 and the transistor Q6 is connected together to the input terminal 1. The node of the transistor Q5 and the transistor Q6 constitutes an output terminal 3 of the circuit. An input signal Vi is applied to the input terminal 1 and an output signal Vo is outputted from the output terminal 3.
FIGS. 2(a) and 2(b) are timing charts in which FIG. 2(a) shows the change in the input signal Vi and FIG. 2(b) shows the change in the output signal Vo in the delay circuit shown in FIG. 1.
The operation of the delay circuit shown in FIG. 1 will be described with reference to FIGS. 2(a) and 2(b). When the input signal Vi applied to the input terminal 1 rises as shown in FIG. 2(a), the channel of the MOS capacitor C1 has been already formed, and the charge is stored in the capacitor C1, so that the output signal Vo falls with a delay from the change of the input signal Vi, as shown in FIG. 2(b). On the other hand, when the input signal Vi falls, the channel of the MOS capacitor C1 is not formed, so that the output signal Vo rises with a slight delay. Therefore, in the delay circuit shown in FIG. 1, an output signal Vo is provided at the output terminal 3 in which the waveform of the fall, i.e., the leading edge (shown in FIG. 2(b) by an arrow P) is much delayed.
FIG. 3 is a schematic diagram showing another example of a conventional delay circuit having a complementary insulated gate device. Compared with the delay circuit shown in FIG. 1, the delay circuit of FIG. 3 comprises a MOS capacitor C2 instead of the MOS capacitor C1 connected between the input terminal 1 and the ground V.sub.ss. The other portions of the delay circuit shown in FIG. 3 are the same as these of FIG. 1, so that the detailed description thereof will be omitted.
FIGS. 4(a) and 4(b) are timing charts in which FIG. 4(a) shows the change of the input signal Vi and FIG. 4(b) shows the change of the output signal Vo of the delay circuit shown in FIG. 3.
The operation of the delay circuit shown in FIG. 3 will be described with reference to FIGS. 4(a) and 4(b). When the input signal Vi applied to the input terminal 1 rises as shown in FIG. 4(a), the channel of the MOS capacitor C2 is not formed, so that the output signal Vo falls being slightly delayed from the change of the input signal Vi, as shown in FIG. 4(b). On the other hand, when the input signal Vi falls, the channel of the MOS capacitor C2 has been already formed, and the charge is stored in the capacitor C2, so that the output signal Vo rises with a delay from the change of the input signal Vi. Therefore, in the inverter circuit shown in FIG. 3, an output signal Vo is provided at the output terminal in which the rising waveform, i.e., the trailing edge (shown in FIG. 4(b) by an arrow Q), is much delayed.
Since the above described two conventional delay circuits having complementary insulated gate devices comprise capacitor means, the rise time or fall time is long in both circuits when the output signal changes.
A prior art of particular interest to the delay circuit of the present invention is in Japanese Patent Laying-Open Gazette No. 293016/1986 entitled "Delay Circuit". The prior art is the same as the inverter circuit of the present invention in an aspect that it comprises a transmission gate connected to a preceding stage of the inverter, but it clearly differs from the delay circuit of the present invention in the following points, that is, the gates of two FETs included in the transmission gate are both connected to an input terminal and that it has a function of a limiter circuit.